1. Field of the Invention
This invention relates to an automatic focus adjusting device and, more particularly, to a device in which focus detecting light is projected onto an object and focus adjustment is in response to a signal based on the light reflected from the object.
2. Description of the Prior Art
An automatic focus adjusting device having a light projecting element for projecting light for focus detection onto an object to be photographed and a light receiving element for receiving the light reflected by the object, for controlling an imaging optical system moving to an in-focus position on the basis of an output signal of the light receiving element, is well known.
Previously disclosed, in U.S. patent application Ser. No. 603,660 filed Apr. 26, 1984, is an automatic focus detecting device in which the above light receiving element is divided into two photo-sensitive areas for receiving reflected light, and output signals of the photo-sensitive areas are detected and processed to compute and control the direction of movement of the imaging optical system (infinity distance direction or nearest distance direction) and the quantity of movement thereof (quantity or time of a current supplied to a motor).
In the automatic focus detecting device having the light projecting element for projecting light onto an object and the light receiving element for receiving the light reflected by the object, quantities of light received by the two photo-sensitive areas are converted into electrical signals. The converted electrical signals are integrated and processed to become output signals VA and VB produced by the photo-sensitive areas, an absolute value signal .vertline.VA-VB.vertline., which is an absolute value of the difference between the output signals VA and VB, and a sum signal VA+VB. On the basis of these signals, signals (DD, LL, HH) are produced for detecting whether an object image formed by a photographic lens is in a near-focus condition, in-focus or out-of-focus. Furthermore, on the basis of these signals (DD, LL, HH), a synchronizing signal SYNC for light emission of the light projecting element, motor driving signals FF, NN and LOW, etc. are controlled by a sequence control circuit.
The electrical circuit arrangement associated with the automatic focus detecting device described above is shown in FIG. 1. A reflected light spot image received at photosensitive areas 6A and 6B of a light receiving element 6, as mentioned in the foregoing, is photo-electrically-converted into light information signals. The light information signals thus obtained are supplied to and sufficiently amplified by amplifiers 101a and 101b. The amplifiers 101a and 101b preferably have a sufficient degree of amplification for the modulated frequency of an infrared ray to form the light spot image, and to have a frequency characteristic of suppressing, as much as possible, the degree of amplification for the frequency of such modulated light such as unnecessary sunlight or commercial light sources. Outputs of the amplifiers 101a and 101b are supplied to synchronized detection circuits 102a and 102b and are subjected to synchronized detection. In this case, the synchronizing signal is of the same frequency as that of a light emission driving signal for a light projecting element 3 and is kept in a constant phase relation thereto. Outputs of the synchronized detection circuits 102a and 102b are integrated by integration circuits 103a and 103b and increase, sometimes gradually, at a rate proportional to the signal intensity of the reflected light spot image. The integrated voltages VA and VB which are obtained from the integration circuits 103a and 103b, respectively, through the above signal processing operation are processed and determined by a computing circuit which will be described later herein, and are thus converted into digital information consisting of some bits.
More specifically, the integrated voltages VA and VB are made into a difference signal VA-VB by a subtracter 104 and into a sum signal VA+VB by an adder 105. The difference signal VA-VB is supplied to an absolute value circuit 106 to produce the signal .vertline.VA-VB.vertline.. The value of this signal .vertline.VA-VB.vertline. is compared with a comparison value VD by a comparator 107 operating as comparison means, and the result of comparison is produced by the comparator 107. The sum signal VA+VB is compared with comparison values VL and VH by comparators 108 and 109 operating as level detecting means, respectively, and comparison results are produced by the comparators 108 and 109. In addition, the integrated voltages VA and VB are compared with each other by a comparator 110, and the comparison result is produced by the comparator 110.
FIG. 2 shows a situation where part of a sequence control circuit 111 is embodied by hardware means. A clock CL determines the minimum period of the sequence control circuit 111 and serves as a signal source for modulation of light emission of the light projecting element 3 and a synchronizing signal SYNC for the synchronized detection circuits 102a and 102b. A counter 236 counts an n-number and produces an output Cn which determines the period of distance measurement and the maximum integration time. Flip-flops 237 and 238 are set by the signals DD and HH, respectively, and are reset by the signal Cn at every period of distance measurement. Respective outputs DDQ and HHQ of the flip-flops 237 and 238 are integration terminating signals. These signals DDQ and HHQ are supplied through an OR circuit 239 to a flip-flop 240 to be held there based on the period of the signal Cn. Inverting output Q of the flip-flop 240 becomes an infinity signal FAR. The signals FAR and DDQ come through an OR circuit 241 to set a flip-flop 242, which then produces a motor rotation signal MO. This flip-flop 242 is also reset by the integration terminating or in-focus signal HHQ. At the time of an in-focus condition, the motor rotation signal MO is inhibited from being produced and a motor 8 is thus stopped. The signal AB is renewed into a signal ABQ by a flip-flop 243 in response to the signal DDQ which represents an out-of-focus condition. In this case, a signal AB becomes true logic at the time of a near-focus condition, i.e. VA&gt;VB. The signals ABQ and FAR become a signal FN indicating the rotating direction of the motor 8 through an OR circuit 244. A final motor driving signal FF (in the direction of an infinity distance position) or NN (in the direction of a close-up distance position) is selected based on the output of an AND circuit 245 which receives the signals FN and MO or the output of an AND circuit 247 which receives the signal FN through a NOT circuit 246 and the signal MO.
Where both the signals DDQ and HHQ are of false logic and are supplied through the OR circuit 239 and NOT circuit 248 to an AND circuit 249, the synchronizing signal SYNC is synchronized with an output CLK of the clock CL which is supplied to the AND circuit 249. An integration resetting signal CLR produced by an OR circuit 250 becomes true logic and remains so until resumption of the next integrating process, after termination of integration is decided jointly by the output of the OR circuit 239 and the signal Cn supplied to the OR circuit 250.
FIG. 3 shows wave forms of FIG. 2 signals observed when the focus changes as follows: A near-focus state.fwdarw.a far-focus state.fwdarw.an in-focus state.fwdarw.an infinity distance state. In near-focusing, the signal DD first rises. At this instant, the signal AB is at a high level. In far-focussing, the signal DD also first rises while the signal AB is at a low level. In the event of an in-focus condition, the signal HH rises. In the event of an infinite distance, the end of a maximum integration time comes before any of the signals rise.
FIG. 4 shows an example in which a micro-computer is used as the sequence control circuit 111 to accomplish control with soft-ware employed in part of the device according to the invention. In this drawing are also shown, by way of example, a light emission driving circuit 112 for the light projecting element 3 and a motor driving circuit 113. Reference numeral 251 identifies a micro-computer (the inside of which is arranged, for example, as shown in FIG. 18). Input terminals of the micro-computer 251 receive the signals DD, AB, LL and HH. From output terminals of the micro-computer 251 are produced the signals SYNC, CLR, FF and NN. Furthermore, a signal LOW for the motor 8 rotation speed control, etc. can be readily added to these signals.
A current flowing to the light projecting element 3 is switched in response to the signal SYNC through transistors 252 and 253.
A current flowing to the motor 8 is switched in response to the signals FF and NN through transistors 254 - 257 to flow either in the forward or reverse direction. A voltage control circuit is composed of transistors 258 and 259 and a diode 260. A voltage applied to the motor 8 is shiftable in two steps in response to the signal LOW. Reference numerals 261 and 262 identify respectively a nearest distance switch and an infinity distance switch. These switches 261 and 262 close when the phototaking optical system reaches the nearest and infinity distance end positions to prevent it from being driven further than these end positions.
FIG. 5 shows the wave forms of the synchronizing signal SYNC and the clearance signal CLR of the circuit 250 of FIG. 2, a light emitting period signal IRED for the light projecting element 3, and integration outputs INT of the integration circuits 103a and 103b of FIG. 1.